In order to achieve a fast product ramp up and a high yield, any standard memory, for example a standard DRAM or embedded DRAM circuit needs intensive testing. A DRAM typically includes redundant wordlines and bitlines, which can be used to repair defective wordlines and bitlines. Most conventional DRAM testing procedures are designed to find all possible storage cell failures. An external tester collects all of the detected failures into a so-called fail bit map. The external tester uses the fail bit map to determine the best use of the aforementioned on-chip redundancy to repair the detected defects.
The interface between an external tester and a DRAM chip (or a chip having an embedded DRAM) has two major limitations. One limitation is the maximum clock frequency that an external tester can apply to the chip, and the other limitation is the number of pins on the chip that are available for use by the external tester. When testing an embedded memory such as an embedded DRAM, the aforementioned pin limitation is the major problem. For example, today's technologies provide very large and wide embedded DRAMs (e.g. up to 32 Mb with a 256 bit data with). The testing of such embedded memory circuits is increasingly becoming the most significant cost driving factor in the total chip cost.
FIG. 1 illustrates a conventional example of testing a DRAM embedded within an integrated circuit, for example an application specific integrated circuit (ASIC). The example of FIG. 1 illustrates a 64 bit DRAM data bus and a 16 bit wide external tester interface. The timing diagram of FIG. 1 illustrates a sequence of read accesses of the embedded DRAM, simplified by only showing the column address (CADD) used to access the DRAM. As mentioned above, the embedded DRAM of the FIG. 1 example has a 64 bit data bus (designated as DQ[63:0]) and, in order to lower the number of pins required for external tester access, the internal 64 bit data bus is multiplexed onto a 16 bit external tester interface (DQ_EXT1[15:0]). Accordingly, four clock cycles of the internal DRAM clock (CLK_INT) are required for the external tester to read out all 64 data bits produced by a single read access of the embedded DRAM. Because the embedded DRAM needs only one cycle of CLK_INT to perform its 64 bit read access, the DRAM remains in an idle mode for the remaining three cycles of CLK_INT required for the external tester to read out all 64 bits.
Another conventional example is illustrated in FIG. 2. In the example of FIG. 2, the activity on the 64 bit DRAM data bus DQ and on the external tester interface DQ_EXT1 is the same as in FIG. 1. However, in the example of FIG. 2, the embedded DRAM remains in the idle state for seven cycles of CLK_INT, because the frequency of CLK_INT is twice that of the external tester clock CLK_EXT. In contrast, in the example of FIG. 1, the external tester clock CLK_EXT has the same frequency as the internal clock CLK_INT of the embedded DRAM. The example of FIG. 2 illustrates that the DRAM can easily operate internally at higher clock frequencies than the highest clock frequency which can be applied by the external tester, this latter external tester clock frequency being limited by factors such as wire, pad and probe needle parasitic (R, L, C). As shown in FIG. 2, even though the embedded DRAM can operate at twice the clock frequency of the external tester, the output data rate at DQ_EXT1 is still limited by the clock CLK_EXT of the external tester. The difference caused by the higher internal clock frequency of FIG. 2 is that the DRAM must remain in its idle mode for seven internal clock cycles between each read access cycle.
The 64-to-16 bit multiplexing and corresponding idle cycles illustrated in FIGS. 1 and 2 disadvantageously limit the speed with which memory testing can be accomplished. This is true whether the internal memory clock has the same frequency or a substantially higher frequency than the test interface clock.
It is therefore desirable to reduce the time required to test embedded memory circuits.
The present invention reduces the time required to test embedded memory circuits by identifying a group of locations within a memory, and compressing the failure information associated with those locations. If the compressed failure information indicates a failure associated with any one of the group of memory locations, then a group of redundant memory circuits respectively associated with the group of memory locations is replaced. Such use of compressed failure information advantageously provides a reduction in the time required for testing an embedded memory circuit.